1. Field of the Invention
The present invention relates to a technique for testing a semiconductor integrated circuit having a flip chip structure.
2. Description of the Related Art
A flip chip is a chip in which terminals called bumps are arranged at regular intervals over the entire chip, and its name is derived from the fact that the chip is flipped when being packed into a package. There are two main types of methods for testing a wafer of such a flip chip (a semiconductor integrated circuit having a flip chip structure).
FIGS. 1A and 1B show conventional wafer test methods for the flip chip. As shown in FIG. 1A, a first test method is a method for performing a test while bringing test terminals PP of a pad contact test jig into contact with test pads PD arranged along an outer periphery of the chip instead of bumps BMP arranged at regular intervals over the entire chip.
As shown in FIG. 1B, a second test method is a method for performing a test while bringing test terminals PB of a bump contact test jig into contact with all of the bumps BMP arranged at regular intervals over the entire chip. Incidentally, in FIG. 1A and FIG. 1B, the shaded bumps BMP are power bumps, and the non-shaded bumps BMP are signal bumps.
Moreover, Japanese Unexamined Patent Application Publication No. 2004-234618 discloses a technique for performing a power noise analysis of a semiconductor device with high accuracy.
In the first test method, although the test cost is low, due to the arrangements of the test pads on the periphery, a voltage drop may occur in the vicinity of the center of the chip if the power consumption of the semiconductor integrated circuit is high, which makes the test unfeasible at worst.
In the second test method, there is no possibility that the voltage drop causes the test to be unfeasible since all of the power bumps are used as power supply ports. However, the second test method has a problem that a dedicated test jig (bump contact test jig) is needed to bring the test terminals into direct contact with the bumps. Furthermore, the number of test terminals increases in proportion to the number of bumps, thereby increasing the test cost. Not to mention, the larger the chip size is, the larger the number of bumps becomes, so that the test cost becomes very high if the chip size is large.